1. Field of the Invention
The present invention relates to an evaluation facilitating circuit for a logic circuit or the like to be packaged on a system LSI, and particularly to the composition of scan paths for serial scanning.
2. Description of the Prior Art
Recently, logic circuits packaged on a system LSI have become large so that there is a problem the length of that the testing time for the logic circuits has become a large portion of the time in the manufacture thereof. A parallel scan method and a serial scan method that are well known in the prior art as an effective method of testing the logic circuits. In the parallel scan method, it is possible to designate addresses of any given registers which are objects of the test in the logic circuit. Accordingly, the method can effectively carry out various tests for the logic circuits. However, it requires many circuit elements for the test alone, and the total size of the system becomes large.
In the serial scan method, addresses of a serial group of registers are conducted so that reading and writing in each register group, comprising a plurality of registers is designated. Since, the address designation is conducted corresponding to each register group, the serial scan method requires relatively few circuit elements for the address designation as compared with the parallel scan method. However, in this case, entire register groups whose addresses are to be designated must be scanned even if it is unnecessary, which takes a great deal of time.
As a countermeasure to solve these problems, a method in which a plurality of scan paths are scanned at the same time by internal buses as a common bus, and the method in which scan paths are provided in respective functional blocks in the logic circuit so that tests for the functional blocks are independently carried out have been implemented.
Generally, the scan path is a wiring through which test data and a result of a functional test operation are transferred to and from a target functional block.
The latter method above-described, that is, the method in which scan paths are provided in the respective functional blocks, is superior in that the functional blocks can be tested independently. However, when the mutual relations among the respective functional blocks are tested as a combinational circuit in which input and output portions of the functional blocks are arranged, dummy test data must be set even in register groups other than those which are objects of the tests on the functional blocks. Accordingly, the test requires a great deal of time.